Unicore32 (32-bit Processor )

32/16-bit ISA
Harvard Architecture, 5-stage pipeline,300MHz@0.18um
Improved DSP instruction

Unicore-F64 (64-bit FP Co-Processor )

64-bit data-path
IEEE 754 standard compliant
5 standard FP exceptions
7-stage arithmetic pipeline

High Speed Cache

8kb, 2-way set-associative ICache
8kb, 4-way set-associative DCache, optional write-back
and write-through strategies
Round Robin cyclic replacement algorithm

Memory Management Unit (MMU)

Separated 64-entry instruction TLB and 64-entry TLB
Various page sizes: 4KB, 16KB, 64KB, 4MB
Hardware fast page searching

JTAG On-chip Debugger

2 hardware breakpoints
JTAG interface and boundary scan structure
Supporting single-step debugging, read/write capability
of internal and external registers

On-chip System Bus

32-bit high speed system bus with burst transmission,
supporting multiple master devices
32-bit peripheral

PCI Bus Bridge Controller

PCI 2.2 standard compliant, 32-bit,33MHz Bus
PCI 2.2 standard master and slave mode
On-chip arbiter, supporting 4 external PCI master devices

10/100M Ethernet MAC Controller

IEEE 802.3 standard compliant
10M/100Mbps data transmission
Full-duplex and half-duplex modes
Standard MII interface
Internal and external loop-back

External Memory Controller

Supporting FLASH, SRAM, ROM
PC133 SDRAM industry standard
DRAM interface
Programmable chip selection logic
Separated address/data bus for FLASH and SDRAM

General Purpose System Control Module

32.768 KHz oscillator RTC
4 timers with watch-dog capability
28 general purpose IO ports
32-bit INTC, 24 internal interrupts and 8 external interrupts
Reset controller
Power management unit, 3 low power modes

Peripheral Controller Module

DMA controller, 6 individual data transmission channels,
fixed priority scheme
2 UART, 16550 compliant
2 Synchronous serial ports, Philips